View Q67006-A5198_1730331.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

decoder for program delivery control and video program system pdc / vps decoder cmos ic p-dip-14-3 p-dso-20-1 features l single-chip receiver for pdc data, broadcast either C in broadcast data service packet (bdsp) 8/30/2 according to ccir teletext system b, or C in dedicated line no. 16 of the vertical blanking interval (vps) l reception of unified date and time (udt) broadcast in bdsp 8/30/1 l low external components count l on-chip data and sync slicer l i 2 c-bus interface for communication with external microcontroller l selection of pdc/vps operating mode software controlled by i 2 c-bus register l pin and software compatible to vps decoder sda 5642 l supply voltage: 5 v 10 % l video input signal level: 0.7 vpp to 1.4 vpp l technology: cmos l package: p-dip-14-3 and p-dso-20-1 l operating temperature range: 0 to 70 c semiconductor group 21 12.94 sda 5648 sda 5648x functional description the cmos circuit sda 5648 is intended for use in video cassette recorders to retrieve control data of the pdc system from the data lines broadcast during the vertical blanking interval of a standard video signal. the sda 5648 is devised to handle pdc data transported either in broadcast data service packet (bdsp) 8/30 format 2 (bytes no. 13 through 25) of ccir teletext system b or in the dedicated data line no. 16 in the case of vps. furthermore it is able to receive the unified date and time (udt) information transmitted in bytes no. 15 through 21 of packet 8/30 format 1. type ordering code package sda 5648 q67000-a5186 p-dip-14-3 sda 5648x Q67006-A5198 p-dso-20-1 tape & reel
sda 5648 sda 5648x semiconductor group 22 pin configuration (top view) operating mode (pdc/vps) is selected by a control register which can be written to via the i 2 c-bus interface. p-dip-14-3 p-dso-20-1
sda 5648 sda 5648x semiconductor group 23 pin definitions and functions pin no. p-dip-14-3 pin no. p-dso-20-1 symbol function 1 v ss ground (0 v) 1 v ssa analog ground (0 v) 2 v ssd digital ground (0 v) 3 n.c. not connected 2 4 scl serial clock input of i 2 c-bus. 3 5 sda serial data input of i 2 c-bus. 4 6 cs0 chip select input determining the i 2 c-bus addresses: 20 h / 21 h , when pulled low 22 h / 23 h , when pulled high. 5 7 vcs video composite sync output from sync slicer used for pll based clock generation. 8 n.c. not connected 6 9 davn data available output active low, when pdc/vps data is received. 7 10 ehb output signaling the presence of the first field active high. 8 11 ti test input; activates test mode when pulled high. 9 12 pd1 phase detector/charge pump output of data pll (dapll). 13 n.c. not connected 10 14 pd2/vco2 connector of the loop filter for the syspll. 11 15 vco1 input to the voltage controlled oscillator #1 of the dapll. 12 16 i ref reference current input for the on-chip analog circuit. 13 17 cvbs composite video signal input. 18 n.c. not connected 14 v dd positive supply voltage (+ 5 v nom.). 19 v ddd positive supply voltage for the digital circuits (+ 5 v nom.). 20 v dda positive supply voltage for the analog circuits (+ 5 v nom.).
sda 5648 sda 5648x semiconductor group 24 block diagram
sda 5648 sda 5648x semiconductor group 25 circuit description referring to the functional block diagram of the pdc / vps decoder, the composite video signal with negative going sync pulses is coupled to the pin cvbs through a capacitor which is used for clamping the bottom of the sync pulses to an internally fixed level. the signal is passed on to the slicer, an analog circuitry separating the sync and the data parts of the cvbs signal, thus yielding the digital composite sync signal vcs and a digital data signal for further processing by comparing those signals to internally generated slicing levels. the output of the sync separator is forwarded, on one hand, to the output pin vcs, and on the other hand, to the clock generator and the timing block. the vcs signal represents a key signal that is used for deriving a system clock signal by means of a pll. the data slicer separates the data signal from the cvbs signal by comparing the video voltage to an internally generated slicing level which is found by averaging the data signal during tv line no. 16 in the vps mode or by averaging the data signal during the clock run-in period of the teletext lines during the data entry window (dew) in pdc mode. the clock generator delivers the system clock needed for the basic timing as well as for the regeneration of the data clock. it is based on two phase locked loops (plls) all parts of which are integrated on chip with the exception of the loop filter components. each of the plls is composed of a voltage controlled oscillator (vco), a phase/frequency detector (pfd), and a charge pump which converts the digital output signals of the pfd to an analog current. that current is transformed to a control voltage for the vco by the off-chip loop filter. the generated vco fre- quencies are 10 mhz and 13.875 mhz for vps mode and pdc mode, respectively. all signals necessary for the control of sync and data slicing as well as for the data acquisition are generated by the timing block. in pdc mode, only teletext rows 8/30 containing broadcast data service package (bdsp) infor- mation are acquired. the relevant bytes of 8/30 format 1 (8/30/1) and 8/30 format 2 (8/30/2) are extracted. the 8/30/1-bytes are stored in the acquisition register in a transparent way without any bit manipulation, whereas the hamming coded bytes of packet 8/30/2 are hamming-checked and bytes with one bit error are corrected. the storage of error free or corrected 8/30/2-data bytes in the transfer register to the i 2 c-bus is signalled by the davn output going low. the reception and storage of 8/30/1- data, however, is not indicated by the davn output. the presence of 8/30/1 data can only be checked by polling the data register via the i 2 c-bus. in vps mode, the extracted data bits of tv line no. 16 are checked for biphase errors. with no biphase errors encountered, the acquired bytes are stored in the transfer register to the i 2 c-bus. that transfer is signalled by a h/l transition of the davn output, as well. in both operating modes data are updated when a new data line has been received, provided that the chip is not accessed via the i 2 c-bus at the same time. a micro controller can read the stored bytes via the i 2 c-bus interface at any time. however, one must be aware that the storage of new data from the acquisition interface is inhibited as long as the pdc decoder is being accessed via the i 2 c-bus. at the end of an i 2 c-bus reading the transfer registers are set to ff (hex) until they are updated by the reception of new data packet contained in the cvbs signal.
sda 5648 sda 5648x semiconductor group 26 i 2 c-bus general information the i 2 c-bus interface implemented on the pdc decoder is a slave transmitter/receiver, i.e., both reading from and writing to the pdc / vps decoder is possible. the clock line scl is controlled only by the bus master usually being a micro controller, whereas the sda line is controlled either by the master or by the slave. a data transfer can only be initiated by the bus master when the bus is free, i.e., both sda and scl lines are in a high state. as a general rule for the i 2 c-bus, the sda line changes state only when the scl line is low. the only exception to that rule are the start condition and the stop condition. further details are given below. the following abbreviations are used: start : start condition generated by master as : ackknowledge by slave am : ackknowledge by master nam : no ackknowledge by master stop : stop condition generated by master chip address there are two pairs of chip addresses, which are selected by the cs0-input pin according to the following table write mode for writing to the pdc decoder, the following format has to be used: data transfer (write mode) step1 : in order to start a data transfer the master generates a start condition on the bus by pulling the sda line low while the scl line is held high. step 2 : the bus master puts the chip address on the sda line during the next eight scl pulses. step 3 : the master releases the sda line during the ninth clock pulse. thus the slave can generate an acknowledge (as) by pulling the sda line to a low level. step 4 : the controller transmits the data byte to set the control register. step 5 : the slave acknowledges the reception of the byte. step 6 : the master concludes the data communication by generating a stop condition. the write mode is used to set the i 2 c-bus control register which determines the operating mode: cs0 input write mode read mode low 20 (hex) 21 (hex) high 22 (hex) 23 (hex) start chipadress white mode as byte set control register as stop
sda 5648 sda 5648x semiconductor group 27 control register default: all bits are set to 0 on power-up. bit 0: determines, which kind of data is accessed via the i 2 c-bus when pdc mode is active. bit 1: determines the operating mode. bits 2 through 7 are used for test purposes. dis: dont care. bits 3 through 7 must not be changed for normal operation by user software! read mode for reading from the pdc decoder, the following format has to be used. bit number 7 6 5 4 3 2 1 0 t4 t3 t2 t1 t0 dis pdc/ vps for1/ for2 value 01 bdsp 8/ 30/ 2 data accessible bdsp 8/ 30/ 1 or header row data accessible (refer to description of bit 2) value 01 vps mode active pdc mode active start chipaddress read mode as 1st byte am last byte nam stop
sda 5648 sda 5648x semiconductor group 28 data transfer (read mode) step1 : to start a data transfer the master generates a start condition on the bus by pulling the sda line low while the scl line is held high. the byte address counter in the decoder is reset and points to the first byte to be output. step 2 : the bus master puts the chip address on the sda line during the next eight scl pulses. step 3 : the master releases the sda line during the ninth clock pulse. thus the slave can generate an acknowledge (as) by pulling the sda line to a low level. at this moment, the slave switches to transmitting mode. step 4 : during the next eight clock pulses the slave puts the addressed data byte onto the sda line. step 5 : the reception of the byte is acknowledged by the master device which, in turn, pulls down the sda line during the next scl clock pulse. by acknowledging a byte, the master prompts the slave to increment its internal address counter and to provide the output of the next data byte. step 6 : steps no. 4 and no. 5 are repeated, until the desired amount of bytes have been read. step 7 : the last byte is output by the slave since it will not be acknowledged by the master. step 8 : to conclude the read operation, the master doesnt acknowledge the last byte to be received. a no acknowledge by the master (nam) causes the slave to switch from transmitting to receiving mode. note that the master can prematurely cease any reading operation by not acknowledging a byte. step 9 : the master gains control over the sda line and concludes the data transfer by generating a stop condition on the bus, i. e., by producing a low/high transition on the sda line while the scl line is in a high state. with the sda and the scl lines being both in a high state, the i 2 c-bus is free and ready for another data transfer to be started. the contents of up to 7 registers (bytes) can be read starting with byte 1 bit 7 (refer to the following table).
sda 5648 sda 5648x semiconductor group 29 order of data output on the i 2 c-bus and bit allocation of the 3 different operating modes i 2 c-bus pdc packet 8/30 vps mode format 1 format 2 byte 1 bit 7 6 5 4 3 2 1 0 byte 15 bit 0 2) 1 2 3 4 5 6 7 byte 16 bit 0 1) 1 2 3 byte 17 bit 0 1 2 3 byte 11 bit 0 2) 1 2 3 4 5 6 7 byte 2 bit 7 6 5 4 3 2 1 0 byte 16 bit 0 1 2 3 4 5 6 7 byte 18 bit 0 1 2 3 byte 19 bit 0 1 2 3 byte 12 bit 0 1 2 3 4 5 6 7 byte 3 bit 7 6 5 4 3 2 1 0 byte 17 bit 0 1 2 3 4 5 6 7 byte 20 bit 0 1 2 3 byte 21 bit 0 1 2 3 byte 13 bit 0 1 2 3 4 5 6 7 byte 4 bit 7 6 5 4 3 2 1 0 byte 18 bit 0 1 2 3 4 5 6 7 byte 22 bit 0 1 2 3 byte 23 bit 0 1 2 3 byte 14 bit 0 1 2 3 4 5 6 7 t 1) message bit numbers according to ebu specification of pdc system. 2) transmission bit number
sda 5648 sda 5648x semiconductor group 30 order of data output on the i 2 c-bus and bit allocation of the 3 different operating modes (contd) i 2 c-bus pdc packet 8/30 vps mode format 1 format 2 byte 5 bit 7 6 5 4 3 2 1 0 byte 19 bit 0 1 2 3 4 5 6 7 byte 14 bit 0 1 2 3 byte 15 bit 0 1 2 3 byte 5 bit 0 1 2 3 4 5 6 7 byte 6 bit 7 6 5 4 3 2 1 0 byte 20 bit 0 1 2 3 4 5 6 7 byte 24 bit 0 1 2 3 byte 25 bit 0 1 2 3 byte 15 bit 0 1 2 3 4 5 6 7 byte 7 bit 7 6 5 4 3 2 1 0 byte 21 bit 0 1 2 3 4 5 6 7 byte 13 bit 0 1 2 3 C set to 1 C set to 1 C set to 1 C set to 1 C set to 1 C set to 1 C set to 1 C set to 1 C set to 1 C set to 1 C set to 1 C set to 1
sda 5648 sda 5648x semiconductor group 31 description of davn and ehb outputs davn (data valid active low) ehb (first field active high) in test mode (i.e. ti = high), both davn and ehb are controlled by the cs0 pin and reproduce the state of the cs0 input. signal output vps mode pdc mode 8/30/2 8/30/1 davn h/l-transition (set low) in line 16 when valid vps data is received in the line carrying valid 8/30/2 data in the line carrying valid 8/30/1 data l/h-transition (set high) at the start of line 16 at the beginning of the next field i.e.,at the start of the next data entry window always set high on power-up or during i 2 c-bus accesses when the bus master doesnt acknowledge in order to generate the stop condition ehb l/h-transition at the beginning of the first field h/l-transition at the beginning of the second field
sda 5648 sda 5648x semiconductor group 32 electrical characteristics absolute maximum ratings t a = 25 c parameter symbol limit values unit test condition min. typ. max. ambient temperature t a 070 c in operation storage temperature t stg C 40 125 c by storage total power dissipation p tot 300 mw power dissipation per output p dq 10 mw input voltage v im C 0.3 6 v supply voltage v dd C 0.3 6 v thermal resistance r th su 80 k/w operating range supply voltage v dd 4.5 5 5.5 v supply current i dd 515ma ambient temperature range t a 070 c characteristics t a = 25 c parameter symbol limit values unit test condition min. typ. max. input signals sda, scl, cs0 h-input voltage v ih 0.7 v dd v dd v l-input voltage v il 0 0.3 v dd v input capacitance c i 10 pf input current i im 10 m a input signal ti h-input voltage v ih 0.9 v dd v dd v l-input voltage v il 0 0.1 v dd v input capacitance c i 10 pf input current i im 10 m a
sda 5648 sda 5648x semiconductor group 33 input signals cvbs (pos. video, neg. sync) video input signal level v cvbs 0.7 1.0 2.0 v synchron signal amplitude v sync 0.15 0.3 1.0 v data amplitude v dat 0.25 1.5 v sync 0.5 1.0 v vps mode pdc mode coupling capacitor c c 33 nf h-input current i ih 10 m a v i =5v l-input current i il C 1000 C 400 C 100 m a v i =0v source impedance r s 250 w leakage resistance at coupling capacitor r c 0.91 1 1.2 m w output signals davn, ehb, vcs h-output voltage v qh v dd C 0.5 v i q = C 100 m a l-output voltage v ql 0.4 v i q = 1.6 ma output signals sda (open-drain-stage) l-output voltage v ql 0.4 v i q = 3.0 ma permissible output voltage 5.5 v pll-loop filter components (see application circuit) resistance at pd2/vco2 r 1 6.8 k w resistance at vco1 r 2 1200 k w attenuation resistance r 3 6.8 k w resistance at pd2/vco2 r 5 1200 k w integration capacitor c 1 2.2 nf integration capacitor c 3 33 nf vco C frequence range adjustment resistance at iref (for bias current adjustment) r 4 100 k w characteristics (contd) t a = 25 c parameter symbol limit values unit test condition min. typ. max.
sda 5648 sda 5648x semiconductor group 34 i 2 c-bus timing all values referred to v ih and v il levels. parameter symbol limit values unit min. max. clock frequency f scl 0 100 khz inactive time prior to new transmission start-up t buf 4.7 m s hold time during start condition t hd;sta 4.0 m s low-period of clock t low 4.7 m s high-period of clock t high 4.0 m s set-up time for data t su;dat 250 ns rise time for sda and scl signal t tlh 1 m s fall time for sda and scl signal t thl 300 ns set-up time for scl clock during stop condition t su;sto 4.7 m s
sda 5648 sda 5648x semiconductor group 35 pdc/vps-receiver application circuit
sda 5648 sda 5648x semiconductor group 36 i 2 c-bus signals during write operations
sda 5648 sda 5648x semiconductor group 37 i 2 c-bus signals during read operations
sda 5648 sda 5648x semiconductor group 38
sda 5648 sda 5648x semiconductor group 39 position of teletext and vps data lines within the vertical blanking interval (shown for first field) definition of voltage levels for vps data line
sda 5648 sda 5648x semiconductor group 40 bdsp 8/30 format 1 bit allocation this corresponds to the coding adopted in ccir teletext system b bdsp 8/30 format 1. nb: the received bytes are output on the i 2 c-bus in a transparent way, i.e., on a bit-first-in-first-out basis. no bit manipulation is performed on the chip in this operating mode. when evaluating the numbers, note that each 4-bit-digit has been incremented by one prior to transmission, and the least significant bits are transmitted first. byte no. bit no. contents 01234567 time offset code 15 weight weight sign 2 C2 2 C1 2 0 2 1 2 2 2 3 0 1 16 mjd digit weight 10 4 1111 modified julian date (mjd) 1. byte 17 mjd digit weight 10 2 mjd digit weight 10 3 modified julian date 2. byte 18 mjd digit weight 10 0 mjd digit weight 10 1 modified julian date (mjd) 3. byte 19 utc hours units utc hours tens universal time coordinated (utc) 1. byte 20 utc minutes units utc minutes tens universal time coordinated 2. byte 21 utc seconds units utc seconds tens universal time coordinated 3. byte
sda 5648 sda 5648x semiconductor group 41 structure of the teletext data packet 8/30 format 2
sda 5648 sda 5648x semiconductor group 42 bdsp 8/30 format 2 bit allocation the four message bits of byte 13 are used as follows: byte 13 bit 0 C lci b 1 ) label channel identifier 1 C lci b 2 ) 2 C luf label update flag 3 C reserved but as yet undefined the message bits of bytes 14 C 25 are used in a way similar to the coding of the label in the dedicated television line as follows: byte 14 bit 0 pcs b 1 ) status of byte 20 bit 0 pil b 15 ) 1 pcs b 2 ) analogue sound 1 pil b 16 ) 2 pil b 17 ) minute 2 ) reserved but yet 3 pil b 18 ) 3 ) undefined byte 21 bit 0 pil b 19 ) 1 pil b 20 ) byte 15 bit 0 cni b 1 ) 1 cni b 2 ) country 2 cni b 5 ) 2 cni b 3 ) 3 cni b 6 ) country 3 cni b 4 ) byte 22 bit 0 cni b 7 ) 1 cni b 8 ) byte 16 bit 0 cni b 9 ) network (or 1 cni b 10 ) program provider) 2 cni b 11 ) 3 cni b 12 ) 2 pil b 1 ) byte 23 bit 0 cni b 13 ) network (or 3 pil b 2 ) 1 cni b 14 ) program byte 17 bit 0 pil b 3 ) day 2 cni b 15 ) provider) 1 pil b 4 ) 3 cni b 16 ) 2 pil b 5 ) byte 24 bit 0 pty b 1 ) 3 pil b 6 ) 1 pty b 2 ) byte 18 bit 0 pil b 7 ) month 2 pty b 3 ) 1 pil b 8 ) 3 pty b 4 ) program 2 pil b 9 ) byte 25 bit 0 pty b 5 ) type 1 pty b 6 ) 3 pil b 10 ) 2 pty b 7 ) byte 19 bit 0 pil b 11 ) 3 pty b 8 ) 1 pil b 12 ) hour 2 pil b 13 ) 3 pil b 14 )
sda 5648 sda 5648x semiconductor group 43 data format of the program delivery data in the dedicated tv line time parameter ? pcs cni cni pil cni pty byte no. ? 1 2 3 & 4 5 6 to 10 11 12 13 14 15 parameter bits b i , i = ? 12341234 9101 2 3 4 5 6 7 8 910111213141516171819205 6 7 81112131415161 2 3 4 5 6 7 8 transmission bit no. ? 01234567 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 bits b 1 and b 2 : 00 dont know 01 mono 10 stereo 11 dual sound bits b 3 and b 4 are reserved ml mlmlmlm lmlm lm l content ? clock run-in start code not relevant to pdc reserved for enhancement of vps not relevant to pdc net. or prog. prov. bin. day binary month binary hour binary minute binary country binary network or program provider binary program type binary reserved code values for receiver control (service codes) timer control code n ....... n n n 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 n ....................................... n a ............................. a record inhibit/term. n ....... n n n 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 n ....................................... n a ............................. a interruption code n ....... n n n 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 n ....................................... n a ............................. a continuation code n ....... n n n 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 n ....................................... n a ............................. a unenhanced vps 1111 n n p ................... ................ ...................... ......................p n ....................................... n a ............................. a pty not in use n ....... n n n p ................... ................ ...................... ......................p n ....................................... n 1 1 1 1 1 1 1 1 abbreviations: cni = country and network identification pcs = program control status pil = program identification label pty = program type m = most-significant bit l = least-significant bit a = bit value is that of the current pty code n = bit value is that of the current cni code p = bit value is that of the current pil code ? ? ? ? ? ? ...... ...... ...... ? ...... ...... . ...... . ...... ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?

▲Up To Search▲

Price & Availability of Q67006-A5198

	To Download Q67006-A5198 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .